In multi-core processors or processing systems, each core may correspond to a cache memory, accessible only by that core. Furthermore, shared cache memory, accessible to all of the cores, may be provided to extend cache capacity.
Cache access time may be affected by propagation delays caused by capacitance of interconnects from a logic circuit, such as a core, to or from the core. In general, cache access time may increase in proportion to such physical properties as the distance between the cache and an accessing logic, the width of the interconnect, etc. Accordingly, some prior art processors may organize a shared cache into multiple chunks and arrange the chunks so that frequently accessed data items are close to the processor(s) (or processing core(s)) that use them.
However, prior art caching schemes for moving frequently accessed items close to an accessing logic (e.g., processor core) may be expensive in terms of energy consumed and/or die area.